1. Field of the Invention
The invention is concerned with interconnect substrates such as a multi-chip substrate (MCS) by which a plurality of integrated chips can be interconnected into a multi-chip module (MCM).
2. Description of the Related Art
It has long been known that by mounting a plurality of integrated chips on an interconnect substrate such as an MCS, faster switching can be achieved by virtue of shorter paths between the chips. An interconnect substrate that includes a multi-level metal-polymer composite is described in Pan et al.: "A Planar Approach to High Density Copper-polyimide Interconnect Fabrication," Proceedings of the Technical Conference, Eighth Annual International Electronics Packaging Conference, Nov. 7-10, 1988, pp 174-189. The Pan publication says:
"In the MCC interconnect fabrication approach, we use pattern electroplating to plate copper to form the conductor layers and the pillar layers. These copper features are overcoated with nickel for enhanced reliability before polyimide is spin coated over the plated features to partially planarize the topography. Mechanical polishing is then carried out to fully planarize the substrate surface and expose the copper pillars. The substrate is then ready for the next layers of conductor and pillar fabrication" (Abstract, p. 174).
The polyimide employed by Pan is formed in situ from a polyamic acid, and its formulation involves the formation of water. The nickel overcoating is necessary to protect the copper features from the polyamic acid and the water that otherwise would corrode the copper. Nevertheless, Pan uses this polyimide, in part because of "its relative ease to form thick coatings and its ability to partially planarize the substrate topography" (p. 176). The final planarization is achieved by mechanical polishing.
The interconnect of the Pan publication is also the subject of U.S. Pat. No. 4,810,332 (Pan) which says that the protective overcoating can be nickel, chromium or any material that can be electroplated, describing at col. 3, lines 27-54, a series of steps for applying the protective overcoating.
Other interconnect substrates are described in U.S. Pat. No. 4,681,795 (Tuckerman); U.S. Pat. No. 4,702,792 (Chow et al.); and U.S. Pat. No. 4,770,897 (Wu). The interconnect substrate of Chow is made using a polymeric photoresist which is patterned to form openings. Conductive material is applied to fill the openings, and excess conductive material is removed by chemical-mechanical polishing to expose at least the exterior major surface of the polymeric material. The surface then has conductive features such as fine lines, patterns, and connectors surrounded by polymeric material. Preferred polymeric photoresists have a Tg of at least 150.degree. C. and include novolaks which have been hard baked and polyimides.
The Tuckerman patent concerns the problem of planarizing the surface of each layer of a multilevel interconnect and does so by melting the metal using a pulsed laser prior to patterning. Because organics such as polyimides might be damaged by momentary exposure to the molten metal, he suggests that the dielectric be pure SiO.sub.2.
The Wu patent concerns enhancing adhesion between a copper conductor and a polyimide dielectric of an interconnect substrate as well as making the copper corrosion resistant. This is done by completely sealing the copper conductor in a cured dielectric sub-layer that has been applied as two materials, both preferably photosensitive polyimides that preferably are cured in a vacuum at a temperature of about 300.degree. or 400.degree. C.
Although small quantities of prototype MCS's have been available from various sources for several years, there has been no large-scale production.